پروژه IIM42352 با میکروکنترلر STM32F303

typedef enum bank_sel
{
BANK_0 = 0 ,
BANK_1     ,
BANK_2     ,
BANK_3     ,
BANK_4
}IIM42352_Bank_Sel;

typedef enum  interface
{
 NOT_SPI = 0,
 IS_SPI
}IIM42352_Interface;

typedef enum packet_to_FIFO
{
NOTHING_To_FIFO    = 0,
ACCEL_TEMP_To_FIFO = 5
}IIM42352_Packet_To_FIFO;

typedef enum Soft_Reset_Config
{
IIM42352_RESET     = 0x01,
IIM42352_NOT_RESET = 0x00,
} IIM42352_Soft_Reset_Config;

typedef enum Pin9_Function
{
INT2   = 0,
FSYNC  = 1,
CLKIN  = 2

} IIM42352_PIN9_FUNCTION;

typedef enum accel_fs_sel
{
FS_16g = 0 ,
FS_8g      ,
FS_4g      ,
FS_2g
}IIM42352_Accel_Fs_Sel;

typedef enum Scale_Factor
{
SCALE_FACTOR_2048_LSB_g  = 2048    ,
SCALE_FACTOR_4096_LSB_g  = 4096    ,
SCALE_FACTOR_8192_LSB_g  = 8192    ,
SCALE_FACTOR_16384_LSB_g = 16384
}IIM42352_Accel_Scale_Factor;

typedef enum accel_odr
{
ODR_32KHz   = 1,
ODR_16KHz   = 2,
ODR_8KHz    = 3,
ODR_4KHz    = 4,
ODR_2KHz    = 5,
ODR_1KHz    = 6,
ODR_200Hz   = 7,
ODR_100Hz   = 8,
ODR_50Hz    = 9,
ODR_25Hz    = 10,
ODR_12Hz5   = 11,
ODR_6Hz25   = 12,
ODR_3Hz125  = 13,
ODR_1Hz5625 = 14,
ODR_500Hz   = 15
}IIM42352_Accel_ODR;

typedef enum FIFO_Config
{
BYPASS = 0 ,
STREAM_TO_FIFO,
STOP_ON_FULL
}IIM42352_FIFO_MODE ;

typedef enum accel_odr
{
ODR_32KHz   = 1,
ODR_16KHz   = 2,
ODR_8KHz    = 3,
ODR_4KHz    = 4,
ODR_2KHz    = 5,
ODR_1KHz    = 6,
ODR_200Hz   = 7,
ODR_100Hz   = 8,
ODR_50Hz    = 9,
ODR_25Hz    = 10,
ODR_12Hz5   = 11,
ODR_6Hz25   = 12,
ODR_3Hz125  = 13,
ODR_1Hz5625 = 14,
ODR_500Hz   = 15
}IIM42352_Accel_ODR;

typedef enum Ability
{
Disable = 0,
Enable
}IIM42352_Ability;

typedef enum
{
LITTLE = 0,
BIG
}IIM42352_Data_Endian;

typedef enum timestamp_resolution
{
_1_uS   = 0,
_16_uS
} IIM42352_Timestamp_Resolution;

typedef enum
{
IN_BYTES = 0,
IN_RECORDS
}IIM42352_FIFO_Counting;

typedef enum UI_Filter_Order
{
_1_ORDER = 0 ,
_2_ORDER     ,
_3_ORDER
}IIM42352_UI_Filter_Order ;

typedef enum Power_Mode
{
IIM42352_LOW_NOISE  = 0x03,
IIM42352_LOW_POWER  = 0x02,
IIM42352_ACCEL_OFF  = 0x01
} IIM42352_Power_Mode;

ypedef enum
{
LN_FILTER_BW_40 = 0x7 ,
LN_FILTER_BW_20 = 0x6 ,
LN_FILTER_BW_16 = 0x5 ,
LN_FILTER_BW_10 = 0x4 ,
LN_FILTER_BW_8  = 0x3 ,
LN_FILTER_BW_5  = 0x2 ,
LN_FILTER_BW_4  = 0x1 ,
LN_FILTER_BW_2  = 0x0
} IIM42352_Low_Noise_Filter_BW;

typedef enum
{
 LP_1x_AVG_FILTER  = 0x1 ,
 LP_16x_AVG_FILTER = 0x6
} IIM42352_Low_Power_Filter_AVG;

typedef enum Preparation
{
IS_NOT_Ready = 0,
IS_Ready
}IIM42352_Preparation;

typedef enum Reset_Status
{
FAILED = 0,
DONE
}IIM42352_Reset_Status;

typedef enum FIFO_Ability
{
FIFO_DISABLE = 0,
FIFO_ENABLE
} IIM42352_FIFO_Ability;

typedef enum Get_DATA
{
FROM_REGISTER = 0,
FROM_FIFO
} IIM42352_Get_DATA;

/********************************************************
 *Declare Read&Write IIM42352 Register Values Functions *
 ********************************************************/
extern	uint8_t	GB_IIM42352_Read_Reg_Data ( uint8_t regAddr, IIM42352_Bank_Sel regBank, uint8_t* data);
extern	uint8_t GB_IIM42352_Read_Reg_Bits (uint8_t regAddr, IIM42352_Bank_Sel regBank, uint8_t start_bit, uint8_t len, uint8_t* data);
extern	uint8_t GB_IIM42352_Burst_Read(uint8_t regAddr, IIM42352_Bank_Sel regBank, uint8_t *data, uint16_t byteQuantity);
extern	uint8_t GB_IIM42352_Write_Reg_Data(uint8_t regAddr, IIM42352_Bank_Sel regBank, uint8_t data);
extern	uint8_t	GB_IIM42352_Write_Reg_Bits(uint8_t regAddr, IIM42352_Bank_Sel regBank, uint8_t start_bit, uint8_t len, uint8_t data);
extern	uint8_t GB_IIM42352_Burst_Write		( uint8_t regAddr, IIM42352_Bank_Sel regBank, uint8_t *data, 	uint16_t byteQuantity);
/********************************************************
 *       Declare IIM42352 Configuration Functions       *
 ********************************************************/
extern void GB_IIM42352_Enable_Disable_XYZ_ACCEL(GebraBit_IIM42352 * IIM42352 ,IIM42352_Ability x_axis,IIM42352_Ability y_axis,IIM42352_Ability z_axis );
extern void GB_IIM42352_Enable_Disable_Temperature(GebraBit_IIM42352 * IIM42352 ,IIM42352_Ability temp );
extern void GB_IIM42352_Set_Sensor_Data_Endian ( GebraBit_IIM42352 * IIM42352 , IIM42352_Data_Endian  data_end  );
extern void GB_IIM42352_Bank_Selection( IIM42352_Bank_Sel bsel);
extern void GB_IIM42352_Who_am_I(GebraBit_IIM42352 * IIM42352);
extern void GB_IIM42352_Select_SPI4_Interface(GebraBit_IIM42352 * IIM42352 , IIM42352_Interface spisel);
extern void GB_IIM42352_Select_PIN9_Function(GebraBit_IIM42352 * IIM42352 ,  IIM42352_PIN9_FUNCTION pin9f);
extern void GB_IIM42352_DISABLE_FSYNC (GebraBit_IIM42352 * IIM42352 ,  IIM42352_Ability able ) ;
extern void GB_IIM42352_DISABLE_RTC_Mode ( void ) ;
extern void GB_IIM42352_SET_Time_Stamp_Register(GebraBit_IIM42352 * IIM42352 ,IIM42352_Ability ability);
extern void GB_IIM42352_Set_Timestamp_Resolution (GebraBit_IIM42352 * IIM42352 ,  IIM42352_Timestamp_Resolution res ) ;
extern void GB_IIM42352_SET_INT_ASYNC_RESET_ZERO(void );
/********************************************************
 *          Declare IIM42352 FIFO Functions             *
 ********************************************************/
extern void GB_IIM42352_FIFO_FLUSH(void );
extern void GB_IIM42352_Set_FIFO_MODE (GebraBit_IIM42352 * IIM42352 , IIM42352_FIFO_MODE mode ) ;
extern void GB_IIM42352_SET_FIFO_Count (GebraBit_IIM42352 * IIM42352 , IIM42352_FIFO_Counting counting , IIM42352_Data_Endian endian ) ;
extern void GB_IIM42352_GET_FIFO_Count(GebraBit_IIM42352 * IIM42352 ) ;
extern void GB_IIM42352_Write_ACCEL_TEMP_To_FIFO(GebraBit_IIM42352 * IIM42352 , IIM42352_Packet_To_FIFO allpack) ;
extern void GB_IIM42352_SET_FIFO_WATERMARK (GebraBit_IIM42352 * IIM42352 ,IIM42352_Ability watermark , uint16_t wm );
extern void GB_IIM42352_SET_FIFO_Decimation_Factor (GebraBit_IIM42352 * IIM42352 ,uint8_t factor );
extern void GB_IIM42352_FIFO_Configuration ( GebraBit_IIM42352 * IIM42352 , IIM42352_FIFO_Ability fifo   ) ;
extern void GB_IIM42352_SET_FIFO_High_Resolution( GebraBit_IIM42352 * IIM42352 ,IIM42352_Ability highres);
extern IIM42352_Preparation GB_IIM42352_Check_FIFO_FULL(GebraBit_IIM42352 * IIM42352);
extern void GB_IIM42352_Read_FIFO(GebraBit_IIM42352 * IIM42352 , uint16_t qty)  ;
/********************************************************
 *          Declare IIM42352 ACCEL Functions             *
 ********************************************************/
extern void GB_IIM42352_Set_ACCEL_FS ( GebraBit_IIM42352 * IIM42352 , IIM42352_Accel_Fs_Sel fs )  ;
extern void GB_IIM42352_Set_ACCEL_ODR ( GebraBit_IIM42352 * IIM42352 , IIM42352_Accel_ODR odr ) ;
extern void GB_IIM42352_UI_Filter_Order (GebraBit_IIM42352 * IIM42352 ,  IIM42352_UI_Filter_Order order ) ;
extern void GB_IIM42352_ACCEL_LN_Filter_Configuration(GebraBit_IIM42352 * IIM42352 , IIM42352_Low_Noise_Filter_BW filter);
extern void GB_IIM42352_ACCEL_LP_Filter_Configuration(GebraBit_IIM42352 * IIM42352 , IIM42352_Low_Power_Filter_AVG filter);
extern void GB_IIM42352_SET_Data_Ready_Interrupt(GebraBit_IIM42352 * IIM42352 ,IIM42352_Ability ability);
extern void GB_IIM42352_SET_FIFO_Full_Interrupt(GebraBit_IIM42352 * IIM42352 , IIM42352_Ability ability);
extern IIM42352_Preparation GB_IIM42352_Check_Data_Preparation(GebraBit_IIM42352 * IIM42352);
extern void GB_IIM42352_Get_Sensor_Data_Endian ( IIM42352_Data_Endian * data_end  ) ;
/********************************************************
 *          Declare IIM42352 DATA Functions             *
 ********************************************************/
extern void GB_IIM42352_Get_Temp_Register_Raw_Data(GebraBit_IIM42352 * IIM42352);
extern void GB_IIM42352_Get_Temp_Register_Valid_Data(GebraBit_IIM42352 * IIM42352);
extern void GB_IIM42352_Get_ACCEL_DATA_X_Register_Raw(GebraBit_IIM42352 * IIM42352);
extern void GB_IIM42352_Get_ACCEL_DATA_Y_Register_Raw(GebraBit_IIM42352 * IIM42352);
extern void GB_IIM42352_Get_ACCEL_DATA_Z_Register_Raw(GebraBit_IIM42352 * IIM42352);
extern void GB_IIM42352_Get_ACCEL_DATA_X_Register_Valid_Data(GebraBit_IIM42352 * IIM42352);
extern void GB_IIM42352_Get_ACCEL_DATA_Y_Register_Valid_Data(GebraBit_IIM42352 * IIM42352);
extern void GB_IIM42352_Get_ACCEL_DATA_Z_Register_Valid_Data(GebraBit_IIM42352 * IIM42352);
extern void GB_IIM42352_Get_Temperature(GebraBit_IIM42352 * IIM42352);
extern void GB_IIM42352_Get_XYZ_ACCELERATION(GebraBit_IIM42352 * IIM42352);
/********************************************************
 *          Declare IIM42352 HIGH LEVEL Functions       *
 ********************************************************/
extern void GB_IIM42352_Format_Data_Base_On_Endian(GebraBit_IIM42352 * IIM42352, const uint8_t *datain, uint16_t *dataout);
extern void GB_IIM42352_Soft_Reset ( GebraBit_IIM42352 * IIM42352 );
extern void GB_IIM42352_Set_Power_Management(GebraBit_IIM42352 * IIM42352 , IIM42352_Power_Mode pmode);
extern void GB_IIM42352_initialize( GebraBit_IIM42352 * IIM42352 );
extern void GB_IIM42352_Configuration(GebraBit_IIM42352 * IIM42352, IIM42352_FIFO_Ability fifo);
extern void GB_IIM42352_Get_ACCEL_XYZ_TEMP_From_Registers(GebraBit_IIM42352 * IIM42352);
extern void GB_IIM42352_Get_ACCEL_XYZ_TEMP_From_FIFO(GebraBit_IIM42352 * IIM42352);
extern void GB_IIM42352_Get_Data(GebraBit_IIM42352 * IIM42352 , IIM42352_Get_DATA get_data);

/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN PTD */
GebraBit_IIM42352 IIM42352_Module;
/* USER CODE END PTD */

GB_IIM42352_initialize( &IIM42352_Module );
GB_IIM42352_Configuration(&IIM42352_Module ,FIFO_ENABLE);
             //GB_IIM42352_Configuration(&IIM42352_Module , FIFO_DISABLE );

GB_IIM42352_Get_Data( &IIM42352_Module , FROM_FIFO );
//GB_IIM42352_Get_Data(  &IIM42352_Module , FROM_REGISTER  );

/* USER CODE BEGIN Header */
/*
 * ________________________________________________________________________________________________________
 * Copyright (c) 2020 GebraBit Inc. All rights reserved.
 *
 * This software, related documentation and any modifications thereto (collectively “Software”) is subject
 * to GebraBit and its licensors' intellectual property rights under U.S. and international copyright
 * and other intellectual property rights laws.
 *
 * GebraBit and its licensors retain all intellectual property and proprietary rights in and to the Software
 * and any use, reproduction, disclosure or distribution of the Software without an express license agreement
 * from GebraBit is strictly prohibited.

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT
 * NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT IN
 * NO EVENT SHALL GebraBit BE LIABLE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES,
 * OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT,
 * NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
 * OF THE SOFTWARE.
 * ________________________________________________________________________________________________________
 */
/**
  ******************************************************************************
  * @file           : main.c
  * @brief          : Main program body
  ******************************************************************************
  * @attention
  *
  * Copyright (c) 2022 STMicroelectronics.
  * All rights reserved.
  *
  * This software is licensed under terms that can be found in the LICENSE file
  * in the root directory of this software component.
  * If no LICENSE file comes with this software, it is provided AS-IS.
  *
  ******************************************************************************
  */
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "main.h"
//#include "i2c.h"
#include "spi.h"
#include "gpio.h"
#include "GebraBit_IIM42352.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */

/* USER CODE END Includes */

/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN PTD */
GebraBit_IIM42352 IIM42352_Module;
/* USER CODE END PTD */

/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN PD */
/* USER CODE END PD */

/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PM */

/* USER CODE END PM */

/* Private variables ---------------------------------------------------------*/

/* USER CODE BEGIN PV */
/* USER CODE END PV */

/* Private function prototypes -----------------------------------------------*/
void SystemClock_Config(void);
/* USER CODE BEGIN PFP */

/* USER CODE END PFP */

/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */

/* USER CODE END 0 */

/**
  * @brief  The application entry point.
  * @retval int
  */
int main(void)
{
  /* USER CODE BEGIN 1 */
  /* USER CODE END 1 */

  /* MCU Configuration--------------------------------------------------------*/

  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
  HAL_Init();

  /* USER CODE BEGIN Init */

  /* USER CODE END Init */

  /* Configure the system clock */
  SystemClock_Config();

  /* USER CODE BEGIN SysInit */

  /* USER CODE END SysInit */

  /* Initialize all configured peripherals */
  MX_GPIO_Init();
  //MX_I2C1_Init();
  MX_SPI1_Init();
	GB_IIM42352_initialize( &IIM42352_Module );
	GB_IIM42352_Configuration(&IIM42352_Module ,FIFO_ENABLE );
	//GB_IIM42352_Configuration(&IIM42352_Module , FIFO_DISABLE );
  /* USER CODE END 2 */
  /* Infinite loop */
  /* USER CODE BEGIN WHILE */

  while (1)
  {

    /* USER CODE END WHILE */
    /* USER CODE BEGIN 3 */
				GB_IIM42352_Get_Data(  &IIM42352_Module , FROM_FIFO  );
		    //GB_IIM42352_Get_Data(  &IIM42352_Module , FROM_REGISTER  );
  }
  /* USER CODE END 3 */
}

/**
  * @brief System Clock Configuration
  * @retval None
  */
void SystemClock_Config(void)
{
  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};

  /** Initializes the RCC Oscillators according to the specified parameters
  * in the RCC_OscInitTypeDef structure.
  */
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
  RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
  {
    Error_Handler();
  }

  /** Initializes the CPU, AHB and APB buses clocks
  */
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;

  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
  {
    Error_Handler();
  }
  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C1;
  PeriphClkInit.I2c1ClockSelection = RCC_I2C1CLKSOURCE_SYSCLK;
  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
  {
    Error_Handler();
  }
}

/* USER CODE BEGIN 4 */

/* USER CODE END 4 */

/**
  * @brief  This function is executed in case of error occurrence.
  * @retval None
  */
void Error_Handler(void)
{
  /* USER CODE BEGIN Error_Handler_Debug */
  /* User can add his own implementation to report the HAL error return state */
  __disable_irq();
  while (1)
  {
  }
  /* USER CODE END Error_Handler_Debug */
}

#ifdef  USE_FULL_ASSERT
/**
  * @brief  Reports the name of the source file and the source line number
  *         where the assert_param error has occurred.
  * @param  file: pointer to the source file name
  * @param  line: assert_param error line source number
  * @retval None
  */
void assert_failed(uint8_t *file, uint32_t line)
{
  /* USER CODE BEGIN 6 */
  /* User can add his own implementation to report the file name and line number,
     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
  /* USER CODE END 6 */
}
#endif /* USE_FULL_ASSERT */